1. Technical Field
The invention relates generally to lock indicator circuits for timing circuits and, more specifically, to frequency-lock indicator circuits used with Phase-Lock Loop or similar oscillation circuits.
2. Background Art
Many different devices need circuits that tracks two clocks and provide an indication when the two are in-phase or have the same frequency. One example of such a circuit is the Phase-Lock Loop (PLL) circuit, which produces an output clock that operates substantially at the same frequency and phase as the input clock. PLL circuits are commonly used in timing applications such as clock generation, clock extraction and synchronizing chip-to-chip communications.
Lock detection circuitry is used with PLL circuits to indicate when the input and output clocks of the PLL circuit are in a locked position, that is, when the frequency or the phase of an output signal matches the frequency or the phase of an input signal. Most lock detection circuitry deal specifically with indicating when both the phases and the frequency of the circuitry are in locked position.
U.S. Pat. No. 5,008,635, "Phase-Lock-Loop Lock Indicator Circuit," (issued April 1991 to Hanke et al. and assigned to Motorola, Inc.), which is hereby incorporated by reference, discloses a lock detection circuit used for indicating when two clocks have the same frequency and phase in a PLL circuit. The PLL circuit includes a Frequency/Phase Detector device that produces output up and down pulse signals. The number of successive logic high output up and down pulse signals are then counted to generate a lock/unlock detector signal. Consequently, using the signals from the Frequency/Phase Detector in the PLL loop limits the lock detector circuit in that it works only with this specific PLL circuit. Furthermore, because both the frequency and the phase of the signals in this reference need to be basically equal before the locked condition is indicated, systems that only need the output and input clocks to be at the same frequency will have to wait longer while their phases align. Hence, the system's performance is degraded.
Examples of similar lock detection circuits may be found in the following United States Patents, which are hereby incorporated by reference: U.S. Pat. No. 4,617,520, "Digital Lock Detector for a Phase-Locked Loop," (issued October 1986 to Levine and assigned to Motorola, Inc.); U.S. Pat. No. 4,866,402, "System to Verify Phase Lock of a Phase Lock Loop," (issued September 1989 to Black and assigned to TI, Inc.); U.S. Pat. No. 4,885,553, "Continuously Adaptive Phase Locked Loop Synthesizer," (issued December 1989 to Hietala et al. and assigned to Motorola Inc.); and U.S. Pat. No. 5,256,989, "Lock Detection for a Phase Lock Loop," (issued October 1993 to Parker et al. and assigned to Motorola, Inc.).
Although the aforementioned patents provide a lock circuit to indicate when the PLL clock signals are in-phase, the signals that are inputted into the lock indicator circuit are usually input at a predetermined frequency. The lock circuits do not indicate when the frequency from one clock signal matches the frequency from a second clock signal if those clock signals are out-of-phase. Thus, the circuits are not immune to phase differences. Also, the signals from the Frequency/Phase Detector in the PLL loop are needed for the aforementioned lock detector circuits, thus limiting each lock detector circuit to work only with its specific PLL circuit. Furthermore, when the signals from the PLL Frequency/Phase Detector are used in the lock detector circuit design, an undesirable loading and/or noise level may affect the operation of the PLL circuit.
Accordingly, a need has developed in the art for a lock indicator circuit that is immune to phase differences, and can be used with any PLL circuit regardless of the specific Frequency/Phase Detector used for that PLL circuit.